Optimization Techniques for Low Power VLSI Design

Kavya R

PG Student [VLSI Design and Embeded Systems], Dept. of ECE, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India


Dr. S.Gayatri

Assistant Professor, Dept. of, ECE

Sri Jayachamarajendra College of Engineering,

Autonomous under VTU, Mysore, Karnataka, India

Abstract– With shrinking technology, as power density (measured in watts per square millimetre) is raising at an alarming rate, power management is becoming an important aspect for almost every category of design and application. Reducing power consumption and over all on chip power management are the key challenges in deep sub micro meter nodes due to increased complexity.


Power management needs to be considered at very early design stages. Also low-power techniques should to be employed at every design stage, from RTL (Register Transfer Level) to GDSII. This survey paper describes the various strategies, methodologies and power management techniques for low power VLSI circuits. Future challenges that must be met by designers to designs low power high performance circuits are also discussed. State-of-the-art optimization methods at different abstraction levels that target design of low power digital VLSI circuits are surveyed.

Keywords— Optimization, low power, power dissipation, power management


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